FIG. 5 is a diagram showing a typical configuration of a SRAM (static random access memory) circuit. As shown in FIG. 5, a SRAM memory cell 1 (configured as a flip-flop) is connected to True/Bar bit lines 4 (True/Bar bit line pair is denoted as “bit line (T/B)”), via access transistors (each access transistor is denoted also as “access Tr”). Each access transistor is composed by an N-channel MOS transistor that has a gate connected to a word line 3. True/Bar bit line pairs 4 are connected to True/Bar IO line pair 6 (True/Bar IO line pair is denoted as “IO line (T/B)), via column selection circuits (Y selectors) 5 (also referred to as “Y switch”) which are selected by a column decoder (not shown). Among a plurality of sets of bit lines (T/B) 4, one pair of bit line (T/B) 4 of a selected column, for which the column selection circuit (Y selector) 5 is turned on, is electrically connected to the IO line (T/B) 6. The word line 3 is driven to High by a word driver (not shown) which is connected to the word line selected by an X address decoder (not shown).
A sense amplifier 7 is differentially connected to the IO line (T/B) 6. Differential outputs of the sense amplifier 7 are supplied to a latch 8. Output (single ended output) of the latch 8 is connected to a RAM data output terminal. Although there is no particular limitation, in the example of FIG. 5, the latch 8 is composed by an SR latch including two 2-input NAND circuits that have respective inputs and outputs thereof cross-connected. That is, True and Bar IO lines 6 are connected respectively to first input terminals of first and second NAND circuits and outputs of the first and second NAND circuits are connected respectively to second input terminals of the second and first NAND circuits. There is provided a write buffer 9 that has an input (single ended input) connected to the RAM data input terminal and has outputs differentially connected to the IO line (T/B) 6. There are also provided P-channel MOS transistors P1 and P2 that have drains connected respectively to True and Bar bit lines 4, sources connected in common to a power supply (precharge power supply potential), and gates connected to a precharge control signal (Precharge). P-channel MOS transistors P1 and P2 compose a precharge circuit of the corresponding bit line (T/B) 4. There is also provided a P-channel MOS transistor P3 that is connected between True and Bar bit lines and that has a gate connected to the precharge control signal (Precharge). P-channel MOS transistor P3 composes an equalizer circuit of the bit line (T/B) 4. There is also provided P-channel MOS transistors P4 and P5 that have drains connected respectively to True and Bar IO lines 6, have sources connected in common to a power supply voltage (precharge power supply voltage), and have gates connected in common to a precharge control signal (Precharge). P-channel MOS transistors P4 and P5 compose a precharge circuit of the IO line (T/B) 6. There is also provided a P-channel MOS transistor P6 that is connected between True IO line and Bar IO line and has gate connected to the precharge control signal (Precharge). P-channel MOS transistor P6 composes an equalizer circuit of the IO line (T/B) 6. In the True and Bar IO lines 6, transfer gates (switches) TGT and TGB are inserted between connection nodes of column selection circuits (Y selectors) 5 that are provided at the ends of respective bit line pairs, and connection nodes between the differential outputs of the write buffer 9 and the True and Bar IO lines 6. Transfer gates TGT and TGB receives in common an inverted signal (a bar above Sense Enable indicates “inverted” version) of a Sense Enable signal controlling activation of the sense amplifier 7 and are on-off controlled based on the inverted signal of Sense Enable signal.
As shown in FIG. 5, the SRAM memory cell 1 includes a flip-flop including two inverters (not shown). Outputs of first and second inverters of the flip-flop are connected to inputs of the second and first inverters of the flip-flop, respectively. Since this configuration is well known, an internal configuration thereof is not shown in FIG. 5. The SRAM memory cell 1 of six transistors configuration, inclusive of two access transistors, includes two inverters, each of which includes a P-channel MOS transistor (load) that has a source connected to a power supply, and an N-channel MOS transistor (also referred to as a “drive transistor”) that has a source connected to GND (ground), has a drain connected to a drain of the P-channel MOS transistor, and has a gate coupled to a gate of the P-channel MOS transistor. The coupled drains of the P-channel MOS transistor and the N-channel MOS transistor of the two inverters (that is, outputs of the two inverters) are connected respectively to one ends of the two access transistors 2, and coupled gates of the P-channel MOS transistor and the N-channel MOS transistor of respective ones of two inverter (that is, inputs of the inverters) are cross connected to the coupled drains of the P-channel MOS transistor and the N-channel MOS transistor of the other inverter (that is, outputs of the other inverters).
When data is read, a bit line pair is selected by the column selection circuit (Y selector) 5, and one pair of bit line (T/B) 4 of the selected column is electrically connected to the IO line (T/B) 6. Differential amplification of differential voltage between True and Bar bit lines 4 of the selected column is performed by the sense amplifier 7 that connected to the IO line (T/B) 6 and the sense amplifier 7 supplies differentially amplified result to the latch 8. Read data is delivered from the RAM data output terminal. With regard to an overall configuration of a clock synchronization type of SRAM, described below, reference is made to the description of Patent Document (FIG. 1 and the like), for example.
In a clock synchronous static memory circuit, a selected word line is raised to High level in synchronization with a clock to turn on access transistors 2 in a memory cell which have gates connected in common to the selected word line. As a result, one of a True bit line and a Bar bit line is pulled down to GND (ground) voltage in response to data held in the memory cell 1. That is, after True and Bar bit lines 4 have been precharged to a power supply voltage, one of True and Bar bit lines is discharged to GND voltage, via the access transistor 2 that is connected to the selected word line and set to an on state and a drive transistor (not shown) in an on state of the memory cell 1 connected between the access transistor 2 and GND. As a result, a voltage difference develops between the True and Bar bit lines 4 (the IO line (T/B) 6 electrically connected to the bit line (T/B) of the selected column). When a Sense Enable signal is in an activated state (for example in High level), the voltage difference between the True IO line and Bar the IO line is amplified differentially by the sense amplifier 7, as a result of which, data of the memory cell 1 connected to the selected bit line (T/B) 4 is read, and data latched by the latch 8 is delivered to the RAM data output terminal.
When the Sense Enable signal is Low, the transfer gates TGT and TGB that are on-off controlled by an inverted signal of the Sense Enable signal, are set to an on state and hence respective potentials of bit line (T/B) 4 selected by the column selection circuit 5 (Y selector) are transferred to the sense amplifier 7 on the IO line (T/B) 6. When the Sense Enable signal is High, the sense amplifier 7 performs a sense amplification operation and the transfer gates TGT and TGB are both set to an off state to disconnect IO line (T/B) 6 from the bit line (T/B) 4 of the selected column. In a state in which the IO line (T/B) 6 are disconnected from the bit line (T/B) 4, the sense amplifier 7 performs differential amplification of potentials of the IO line (T/B) 6 to which the potentials of the bit line (T/B) 4 of the selected column have been transferred.
The precharge control signal (Precharge) is set to Low before the selected word line is raised and the P-channel MOS transistors P1, P2 and P3 are turned on. P-channel MOS transistors P1 and P2 perform precharging of the bit line (T/B) to the power supply voltage and P-channel MOS transistor P3 performs equalizing of the bit lines (T/B) 4. Precharging and equalizing operation is carried out also for the IO line (T/B) 6, in the same way (at the same timing) as the bit line (T/B) 4 by the P-channel MOS transistors P4, P5 and P6 which are turned on by the precharge control signal (Precharge).
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-11-238381
[Patent Document 2]
JP Patent Kokai Publication No. JP-P2003-45190A